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-- Company: 
-- Engineer:
--
-- Create Date:   15:26:17 04/13/2012
-- Design Name:   InterruptREG
-- Module Name:   C:/Xilinx92i/PROJECTAIC/tb_interruptREG.vhd
-- Project Name:  PROJECTAIC
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: InterruptREG
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_arith.all;

ENTITY tb_interruptREG_vhd IS
END tb_interruptREG_vhd;

ARCHITECTURE behavior OF tb_interruptREG_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT InterruptREG
	PORT(
		clk : IN std_logic;
		pc_in : IN std_logic_vector(9 downto 0);
		ZF : IN std_logic;
		CF : IN std_logic;
		interrupt_read : IN std_logic;
		interrupt_store : IN std_logic;          
		pc_out : OUT std_logic_vector(9 downto 0);
		int_ZF : OUT std_logic;
		int_CF : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL ZF :  std_logic := '0';
	SIGNAL CF :  std_logic := '0';
	SIGNAL interrupt_read :  std_logic := '0';
	SIGNAL interrupt_store :  std_logic := '0';
	SIGNAL pc_in :  std_logic_vector(9 downto 0) := (others=>'0');

	--Outputs
	SIGNAL pc_out :  std_logic_vector(9 downto 0);
	SIGNAL int_ZF :  std_logic;
	SIGNAL int_CF :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: InterruptREG PORT MAP(
		clk => clk,
		pc_in => pc_in,
		ZF => ZF,
		CF => CF,
		interrupt_read => interrupt_read,
		interrupt_store => interrupt_store,
		pc_out => pc_out,
		int_ZF => int_ZF,
		int_CF => int_CF
	);

	clk <= not clk after 25 ns; -- reloj de periodo 50 ns

	tb : PROCESS
		variable old_pc_in : std_logic_vector (9 downto 0);		
	
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 49 ns;
		
--es condicion necesaria que se entre por primera vez
--en el if de interrupt_store		
		pc_in <= conv_std_logic_vector(127,10);
		old_pc_in := pc_in;		
		ZF <= '0';
		CF <= '0';
		interrupt_read <= '0';
		interrupt_store <= '1';								
		
		wait for 50 ns;
		
		interrupt_read <= '1';
		interrupt_store <= '0';
		
		pc_in <= conv_std_logic_vector(0,10);
		
		wait for 50 ns;

--este assert salta y no sabemos por que. Aparentemente, si
-- tiene el comportamiento deseado aunque falle el assert
--revisar.		
		assert(pc_out = old_pc_in)
			report "Error en la actualizacion del PC"
			severity FAILURE;

		report ("**********TESTS DE INTERRUPTREG SUPERADOS**********")
		 severity NOTE;					

		wait; -- will wait forever
	END PROCESS;

END;
